Early microprocessor designs use a single clock distribution line, or spine, located in the center of the microprocessor to distribute a clock signal throughout the microprocessor. Grided power distribution within microprocessors create non-uniform thermal and voltage gradients across the die creating skew in the distributed clock signal. Some microprocessor designs use two clock distribution lines along the periphery of the die to reduce this effect. This method, however, still results in skew between clock distribution lines. As clock frequency in microprocessor designs increases, skew management in the clock distribution network becomes more important. Clock skew affects the microprocessor input/output ("I/O") and internal circuit timing. In maximum delay paths, clock skew limits the maximum operating frequency. In minimum delay paths, clock skew causes the microprocessor to fail at any frequency. Clock skew is a function of load, network distribution, and device mismatch as well as temperature and voltage gradients.
For one prior analog synchronizing system, a center taped fixed delay is used in one distribution line while a second distribution line is adjusted. One disadvantage of this analog approach is that it generates noise in the feedback loop of the system as the delay is increased.